26 lines
503 B
Verilog
26 lines
503 B
Verilog
// Check that variable initialization as part of the declaration works as
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// expected in class methods.
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module test;
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class C;
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task t(bit check);
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int x = 10; // The initialization should happen on each invocation
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if (check) begin
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if (x === 10) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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x = 20;
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endtask
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endclass
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initial begin
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C c;
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c = new;
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c.t(1'b0);
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c.t(1'b1);
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end
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endmodule
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