32 lines
354 B
Verilog
32 lines
354 B
Verilog
// Check that an object can be assigned to a variable of its base class type
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module test;
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class B;
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int x;
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task t;
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$display("PASSED");
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endtask
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endclass
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class C extends B;
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int y;
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task t;
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$display("FAILED");
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endtask
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endclass
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B b;
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C c;
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initial begin
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c = new;
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b = c;
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b.t;
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end
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endmodule
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