69 lines
1.8 KiB
Verilog
69 lines
1.8 KiB
Verilog
module test();
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typedef bit [63:0] bit64;
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typedef logic [63:0] vec64;
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byte byte_array [];
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bit [15:0] bit_array [];
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logic [31:0] vec_array [];
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real real_array [];
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bit64 bit_result;
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vec64 vec_result;
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reg failed = 0;
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initial begin
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byte_array = new [8];
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foreach (byte_array[i]) byte_array[i] = i*16 + i;
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bit_result = bit64'(byte_array);
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$display("%h", bit_result);
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if (bit_result !== 64'h0011223344556677) failed = 1;
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vec_result = vec64'(byte_array);
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$display("%h", vec_result);
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if (vec_result !== 64'h0011223344556677) failed = 1;
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bit_array = new [4];
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foreach (bit_array[i]) bit_array[i] = i*4096 + i*256 + i*16 + i;
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bit_result = bit64'(bit_array);
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$display("%h", bit_result);
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if (bit_result !== 64'h0000111122223333) failed = 1;
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vec_result = vec64'(bit_array);
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$display("%h", vec_result);
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if (vec_result !== 64'h0000111122223333) failed = 1;
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vec_array = new [2];
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vec_array[0] = 32'b01xz_0001_0010_0011_0100_0101_0110_0111;
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vec_array[1] = 32'b1000_1001_1010_1011_1100_1101_1110_1111;
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bit_result = bit64'(vec_array);
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$display("%h", bit_result);
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if (bit_result !== 64'b0100_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111) failed = 1;
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vec_result = vec64'(vec_array);
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$display("%h", vec_result);
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if (vec_result !== 64'b01xz_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111) failed = 1;
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real_array = new [1];
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real_array[0] = 1.2345678;
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bit_result = bit64'(real_array);
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$display("%h", bit_result);
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if (bit_result !== $realtobits(1.2345678)) failed = 1;
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vec_result = vec64'(real_array);
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$display("%h", vec_result);
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if (vec_result !== $realtobits(1.2345678)) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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