17 lines
314 B
Verilog
17 lines
314 B
Verilog
// Check that continuous assignment of two compatible arrays is supported, even
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// if the upper and lower bounds of the arrays are not identical, as long as the
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// size is the same.
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module test;
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wire [1:0] x[1:0];
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wire [1:0] y[2:1];
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assign x = y;
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initial begin
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$display("PASSED");
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end
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endmodule
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