48 lines
818 B
Verilog
48 lines
818 B
Verilog
module main;
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struct packed {
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bit [7:0][7:0] a;
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bit [15:0] b;
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} foo;
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struct packed {
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bit [0:7] [7:0] a;
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bit [0:15] b;
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} bar;
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initial begin
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foo = '0;
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foo.a[2:1] = 16'h1234;
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foo.a[5] = 8'h42;
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foo.a[7] = '1;
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foo.a[7][1:0] = '0;
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foo.b = '1;
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foo.b[1:0] = '0;
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$display("foo = %h", foo);
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bar = '0;
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bar.a[5:6] = 16'h1234;
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bar.a[2] = 8'h42;
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bar.a[0] = '1;
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bar.a[0][1:0] = '0;
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bar.b = '1;
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bar.b[14:15] = '0;
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$display("bar = %h", bar);
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if (foo !== 80'hFC00_4200_0012_3400_FFFC) begin
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$display("FAILED -- foo=%h", foo);
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$finish;
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end
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if (foo !== bar) begin
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$display("FAILED -- bar != foo");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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