36 lines
984 B
Verilog
36 lines
984 B
Verilog
// Released under GPL 2.0
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// (C) 2002 Tom Verbeure
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module main;
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initial begin
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$display("============================");
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$display(">|This is a test|");
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$display("*|%s|", "This is a test");
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$display("*|", "This is a test", "|");
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$display(">| 65|");
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$display("*|%d|", "A");
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$display(">|16706|");
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$display("*|%d|", "AB");
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$display(">| 4276803|");
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$display("*|%d|", "ABC");
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$display(">|1094861636|");
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$display("*|%d|", "ABCD");
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$display(">|01000001|");
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$display("*|%b|", "A");
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$display(">|01000001010000100100001101000100|");
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$display("*|%b|", "ABCD");
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$display(">|01000001010000100100001101000100010010000100100101001010010010110100110001001101010011100100111101010000010100010101001001010011|");
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$display("*|%b|", "ABCDHIJKLMNOPQRS");
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$display(">|41|");
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$display("*|%h|", "A");
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$display(">|41424344|");
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$display("*|%h|", "ABCD");
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$display(">|4142434448494a4b4c4d4e4f50515253|");
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$display("*|%h|", "ABCDHIJKLMNOPQRS");
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end
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endmodule
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