112 lines
2.6 KiB
Verilog
112 lines
2.6 KiB
Verilog
module test();
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function [31:0] cast_4uu(input [5:0] value);
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cast_4uu = 4'(value) + 'd0;
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endfunction
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function [31:0] cast_4us(input [5:0] value);
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cast_4us = 4'(value) + 'sd0;
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endfunction
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function [31:0] cast_4su(input signed [5:0] value);
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cast_4su = 4'(value) + 'd0;
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endfunction
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function [31:0] cast_4ss(input signed [5:0] value);
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cast_4ss= 4'(value) + 'sd0;
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endfunction
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function [31:0] cast_6uu(input [5:0] value);
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cast_6uu = 6'(value) + 'd0;
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endfunction
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function [31:0] cast_6us(input [5:0] value);
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cast_6us = 6'(value) + 'sd0;
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endfunction
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function [31:0] cast_6su(input signed [5:0] value);
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cast_6su = 6'(value) + 'd0;
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endfunction
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function [31:0] cast_6ss(input signed [5:0] value);
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cast_6ss= 6'(value) + 'sd0;
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endfunction
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function [31:0] cast_8uu(input [5:0] value);
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cast_8uu = 8'(value) + 'd0;
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endfunction
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function [31:0] cast_8us(input [5:0] value);
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cast_8us = 8'(value) + 'sd0;
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endfunction
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function [31:0] cast_8su(input signed [5:0] value);
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cast_8su = 8'(value) + 'd0;
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endfunction
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function [31:0] cast_8ss(input signed [5:0] value);
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cast_8ss= 8'(value) + 'sd0;
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endfunction
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localparam [31:0] result1a = cast_4uu(6'h3f);
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localparam [31:0] result1b = cast_4us(6'h3f);
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localparam [31:0] result1c = cast_4su(6'h3f);
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localparam [31:0] result1d = cast_4ss(6'h3f);
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localparam [31:0] result2a = cast_6uu(6'h3f);
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localparam [31:0] result2b = cast_6us(6'h3f);
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localparam [31:0] result2c = cast_6su(6'h3f);
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localparam [31:0] result2d = cast_6ss(6'h3f);
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localparam [31:0] result3a = cast_8uu(6'h3f);
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localparam [31:0] result3b = cast_8us(6'h3f);
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localparam [31:0] result3c = cast_8su(6'h3f);
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localparam [31:0] result3d = cast_8ss(6'h3f);
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reg failed = 0;
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initial begin
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$display("%h", result1a);
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if (result1a !== 32'h0000000f) failed = 1;
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$display("%h", result1b);
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if (result1b !== 32'h0000000f) failed = 1;
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$display("%h", result1c);
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if (result1c !== 32'h0000000f) failed = 1;
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$display("%h", result1d);
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if (result1d !== 32'hffffffff) failed = 1;
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$display("%h", result2a);
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if (result2a !== 32'h0000003f) failed = 1;
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$display("%h", result2b);
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if (result2b !== 32'h0000003f) failed = 1;
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$display("%h", result2c);
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if (result2c !== 32'h0000003f) failed = 1;
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$display("%h", result2d);
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if (result2d !== 32'hffffffff) failed = 1;
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$display("%h", result3a);
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if (result3a !== 32'h0000003f) failed = 1;
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$display("%h", result3b);
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if (result3b !== 32'h0000003f) failed = 1;
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$display("%h", result3c);
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if (result3c !== 32'h000000ff) failed = 1;
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$display("%h", result3d);
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if (result3d !== 32'hffffffff) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule // main
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