63 lines
1.5 KiB
Verilog
63 lines
1.5 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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//
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// SDW - Simple parameter declaration
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//
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// D: Declare a parameter value, then assign it to a variable.
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// D: Check the value of the variable.
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//
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module main();
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parameter VAL_1 = 16'h0001;
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parameter VAL_2 = 16'h5432;
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reg [15:0] test_var;
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initial // Excitation block
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begin
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test_var = VAL_1 ;
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#5 ;
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test_var = VAL_2 ;
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#5 ;
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end
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initial // Validation block
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begin
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#1 ;
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if(test_var != 16'h0001)
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begin
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$display("FAILED - param 1st assign didn't work\n");
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$finish ;
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end
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#5 ;
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if(test_var != 16'h5432)
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begin
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$display("FAILED - param 2nd assign didn't work\n");
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$finish ;
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end
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$display("PASSED\n");
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$finish ;
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end
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endmodule
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