116 lines
3.0 KiB
Verilog
116 lines
3.0 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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//
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// SDW - Validate always with OR, posedge constructs.
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//
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// D: New test used to validate always @(value), and
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// D: always @(val1 or val2), and always @(posedge val1 or negedge val2)
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// D: statements.
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//
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//
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module main ();
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reg working;
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reg val1, val2, val3, val4, val5;
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reg clock ;
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reg test_var;
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initial // Used to generate timing of events
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begin
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val2 = 0;
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val3 = 0;
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val4 = 1;
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# 1;
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test_var = 1;
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# 1;
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val1 = 1; // Cause a change in val1 -> test_var to 0.
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# 2 ; // 4ns
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test_var = 1;
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# 1 ; // 5ns
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val2 = 1; // Cause posedge on val2 -> test_var to 0
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# 2; // 7ns
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test_var = 1;
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# 1; // 8ns
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val4 = 0; // Cause negedge on val4 -> test_var to 0
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# 2; // 10ns
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test_var = 1;
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# 1; // 11 ns
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val3 = 1; // Cause val3 change for always @(a or b)
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# 2; // 13 ns
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test_var = 1;
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# 1; // 14 ns
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val5 = 1; // Cause val5 cahnge for always @(a or b)
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# 2; // 16 ns
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end
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always @(val1) // Val1 changing clears test_var
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test_var = 0;
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always @(posedge val2 or negedge val4)
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test_var = 0;
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always @(val3 or val5)
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test_var = 0;
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initial // This is the validation block
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begin
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# 3; // 3 ns Check always @(val)
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if(test_var)
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begin
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$display("FAILED - always @(val) wrong \n");
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$finish ;
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end
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# 3; // 6 ns Check posedge of always @(posedge val or negedge)
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if(test_var)
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begin
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$display("FAILED - posedge of always @(posedge or negedge) wrong \n");
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$finish ;
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end
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# 3; // 9 ns Check negedge of always @(posedge val or negedge)
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if(test_var)
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begin
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$display("FAILED - negedge of always @(posedge or negedge) wrong \n");
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$finish ;
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end
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# 3; // 12 ns Check a of always @(a or b)
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if(test_var)
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begin
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$display("FAILED - a of always @(a or b) wrong \n");
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$finish ;
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end
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# 3; // 15 ns Check b of always @(a or b)
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if(test_var)
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begin
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$display("FAILED - b of always @(a or b) wrong \n");
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$finish ;
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end
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$display("PASSED\n");
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$finish;
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end
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always @ (posedge clock)
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working = 1;
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always @ (negedge clock)
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working = 1;
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endmodule
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