79 lines
1.9 KiB
Verilog
79 lines
1.9 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate always block instantiation.
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//
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// D: Test validate others versions of always block
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// D: including posedge, negedge.
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//
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//
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module main ();
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reg working;
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reg clock ;
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initial // Used to generate timing of events
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begin
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working = 0;
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clock = 0;
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#4 ;
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working = 0;
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#1 ;
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clock = 1; // 1ns between setting working and clock edge.
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#4 ;
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working = 0;
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#1 ;
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clock = 0; // 1ns between setting working and clock edge.
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#5 ;
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end
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always #2
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working = 1 ;
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initial // This is the validation block
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begin
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# 3; // Check #2 always at 3ns
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if(!working)
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begin
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$display("FAILED - delayed always\n");
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$finish ;
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end
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# 3; // Check posedge at 6 ns
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if(!working)
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begin
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$display("FAILED - posedge always\n");
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$finish ;
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end
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# 7; // Check negedge at 11ns
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if(!working)
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begin
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$display("FAILED - posedge always\n");
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$finish ;
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end
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$display("PASSED\n");
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$finish;
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end
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always @ (posedge clock)
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working = 1;
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always @ (negedge clock)
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working = 1;
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endmodule
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