67 lines
2.2 KiB
Verilog
67 lines
2.2 KiB
Verilog
module test();
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localparam [7:0] dly1 = 4;
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wire [7:0] dly2 = 3;
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reg [7:0] dly3 = 2;
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reg i;
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wire [6:1] o;
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nmos #(dly1, dly2, dly3) buf1(o[1], i, 1'b1);
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nmos #(dly2, dly3, dly1) buf2(o[2], i, 1'b1);
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nmos #(dly3, dly1, dly2) buf3(o[3], i, 1'b1);
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nmos #(dly2-1, dly2-2, dly2-3) buf4(o[4], i, 1'b1);
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nmos #(dly3+1, dly3+2, dly3+3) buf5(o[5], i, 1'b1);
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nmos #(4, 3, 2) buf6(o[6], i, 1'b1);
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function check(input o1, input o2, input o3, input o4, input o5, input o6);
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begin
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check = (o[1] == o1) && (o[2] == o2) && (o[3] == o3)
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&& (o[4] == o4) && (o[5] == o5) && (o[6] == o6);
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end
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endfunction
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reg failed = 0;
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initial begin
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#1 $monitor($time,,i,,o[1],,o[2],,o[3],,o[4],,o[5],,o[6]);
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i = 1'b1;
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#0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bx, 1'bx, 1'b1, 1'b1, 1'bx, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bx, 1'b1, 1'b1, 1'b1, 1'b1, 1'bx)) failed = 1;
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#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
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i = 1'b0;
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#0 if (!check(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1)) failed = 1;
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#1; #0 if (!check(1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1;
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#1; #0 if (!check(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1)) failed = 1;
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#1; #0 if (!check(1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0)) failed = 1;
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#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0)) failed = 1;
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i = 1'bx;
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#0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1;
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#1; #0 if (!check(1'b0, 1'b0, 1'b0, 1'bx, 1'b0, 1'b0)) failed = 1;
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#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'b0, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
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i = 1'bz;
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#0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bx, 1'bx, 1'bx, 1'bz, 1'bx, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx)) failed = 1;
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#1; #0 if (!check(1'bz, 1'bx, 1'bx, 1'bz, 1'bx, 1'bz)) failed = 1;
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#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bx, 1'bz)) failed = 1;
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#1; #0 if (!check(1'bz, 1'bz, 1'bz, 1'bz, 1'bz, 1'bz)) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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