36 lines
630 B
Verilog
36 lines
630 B
Verilog
/*
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* This tests the case that a delay value is a calculated real value.
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*/
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module main;
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real test;
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wire [3:0] Q;
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reg [3:0] D;
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assign #(test/2.0) Q = D;
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initial begin
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test = 4.0;
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D = 1;
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#(test) if (Q !== 1) begin
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$display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D);
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$finish;
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end
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D = 2;
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#(test/4) if (Q !== 1) begin
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$display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D);
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$finish;
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end
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#(test/2) if (Q !== 2) begin
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$display("FAILED -- %0t: Q=%d, D=%d", $time, Q, D);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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