38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
//
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// Copyright (c) 1999 Peter Monta (pmonta@imedia.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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module main;
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wire [3:0] b;
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reg [1:0] a;
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reg c;
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assign b = c<<a;
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initial begin
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#1 ;
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c = 1'b1;
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a = 2'd2;
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#1;
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if (b===4'b0100)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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