23 lines
530 B
Verilog
23 lines
530 B
Verilog
/*
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* This test file is based on PR991.
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*/
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module bug();
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wire _d1,_d2,test,test1,test2,test3;
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assign _d1 = 1;
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assign _d2 = 0;
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assign test = (_d1 && _d2) != 0;
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assign test1 = (_d1 && _d2) == 0;
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assign test2 = (_d1 && _d2) !== 0;
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assign test3 = (_d1 && _d2) === 0;
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initial begin
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#1;
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$displayb(_d2); // Should be 0
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$displayb(test); // Should be 0 (1 && 0) != 0 --> 0 != 0
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$displayb(test1); // Should be 1
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$displayb(test2); // Should be 0
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$displayb(test3); // Should be 1
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end
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endmodule
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