24 lines
372 B
Verilog
24 lines
372 B
Verilog
/*
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* This is a reuced version of PR#990, that captures the essence.
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* Or at least the bug being reported.
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*/
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module bug();
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reg [31:0] x;
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wire y;
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assign y = x == 0;
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initial begin
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$display("y: %b", y);
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x = 0;
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#0;
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$display("y: %b", y);
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if (y === 1'b1) // if x is 0, then x==0 is 1.
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule // bug
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