46 lines
1.0 KiB
Verilog
46 lines
1.0 KiB
Verilog
`define ADDR_DEC_W 8 // Number of bits used to decode.
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`define ADDR_DEVICE0 `ADDR_DEC_W'h10 // Device 0 located at address 20xx_xxxxh
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`define ADDR_DEVICE1 `ADDR_DEC_W'h1F // Device 1 located at address 20xx_xxxxh
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module top ( ) ;
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// Instantiation of the module
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//
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child_module #(`ADDR_DEC_W, `ADDR_DEVICE0, `ADDR_DEVICE1) my_module ( );
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initial begin
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#1 ;
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end
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endmodule
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module child_module ( );
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// Parameters:
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parameter dec_addr_w = 4 ;
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parameter t0_addr = 4'd0 ;
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parameter t1_addr = 4'd0 ;
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// Instantiation of the grandchild module
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//
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grandchild_module #(dec_addr_w, t0_addr, t1_addr) my_grandchild_module ( );
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initial begin
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$display ("CHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ;
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end
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endmodule
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module grandchild_module ( );
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// Parameters:
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parameter dec_addr_w = 4 ;
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parameter t0_addr = 4'd0 ;
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parameter t1_addr = 4'd0 ;
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initial begin
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$display ("GRANDCHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ;
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end
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endmodule
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