22 lines
377 B
Verilog
22 lines
377 B
Verilog
/*
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* Based on PR#941.
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* This tests that trivial contant expressions passed as input to
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* user defined tasks will work. A possible bug would be that the
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* addition expression gets useless code generated.
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*/
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module test;
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task foo;
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input [16:0] in1;
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begin
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$display("%d", in1);
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$display("PASSED");
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end
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endtask
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initial begin
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foo(16'h00 + 'h00);
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end
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endmodule
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