27 lines
342 B
Verilog
27 lines
342 B
Verilog
/*
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* Based on PR#872
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*/
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module main;
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wire test;
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foo u1(test);
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initial begin
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#1 if (test !== 0) begin
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$display("FAILED -- foo.bar == %b (%b)", test, u1.bar);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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/*
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* This the this syntax I'm testing.
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*/
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module foo (output reg bar = 0);
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endmodule
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