18 lines
371 B
Verilog
18 lines
371 B
Verilog
/*
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* Based on pr#859.
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* This test makes sure the @* input search can handle null
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* statements within case alternatives.
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*/
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module test(output reg [15:0] probe_data,input wire [3:0] probe_sel);
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always @*
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case(probe_sel)
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4'h0 :;
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default : probe_data = 16'b0;
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endcase // case(probe_sel)
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initial #1 $display("PASSED");
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endmodule // test
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