77 lines
1.2 KiB
Verilog
77 lines
1.2 KiB
Verilog
/* Extracted from PR#820. */
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module main();
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wire clk;
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wire reset;
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reg [3:0] waddr, raddr;
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reg [7:0] wdata;
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wire [7:0] rdata;
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clk_reset_gen cg(clk, reset);
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ram_rw #(8,4) r(clk, waddr, wdata, 1'b1, raddr, rdata);
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initial begin
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waddr = 4'd0;
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raddr = 4'd14;
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wdata = 0;
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#3001;
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$finish(0);
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end
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always @(posedge clk) begin
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waddr <= #1 waddr + 1;
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raddr <= #1 raddr + 1;
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wdata <= #1 wdata + 3;
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end
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always @(posedge clk)
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$display($time,,"waddr wdata %d %d raddr rdata %d %d",waddr,wdata,raddr,rdata);
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endmodule
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module ram_rw(clk,waddr,wdata,we,raddr,rdata);
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parameter WDATA = 8;
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parameter WADDR = 11;
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input clk;
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input [(WADDR-1):0] waddr;
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input [(WDATA-1):0] wdata;
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input we;
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input [(WADDR-1):0] raddr;
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output [(WDATA-1):0] rdata;
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//local
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reg [(WDATA-1):0] mem[0:((1<<WADDR)-1)];
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reg [(WADDR-1):0] qraddr;
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always @(posedge clk) begin
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qraddr <= #1 raddr;
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if (we)
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mem[waddr] <= #1 wdata;
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end
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assign rdata = mem[qraddr];
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endmodule
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module clk_reset_gen(clk, reset);
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output clk;
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output reset;
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reg clk;
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reg reset;
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initial begin
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reset = 1;
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#5;
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clk = 0;
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#5;
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clk = 1;
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#5;
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reset = 0;
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clk = 0;
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forever #5 clk = ~clk;
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end
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endmodule
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