20 lines
291 B
Verilog
20 lines
291 B
Verilog
/*
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* From PR#751.
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* The (*) can get tangled with a contracted (* *)
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*/
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module tb;
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reg [1:0] sel;
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reg [0:3] in;
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reg out;
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always @(*)
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out = in[sel];
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initial
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begin
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$monitor($time, " %b[%b]: %b", in, sel, out);
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#10 in = 4'b 0100;
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#10 sel = 0;
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#10 sel = 1;
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#10 $finish(0);
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end
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endmodule
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