85 lines
2.1 KiB
Verilog
85 lines
2.1 KiB
Verilog
module signed_multiplier_test;
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reg failed_flag = 0;
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reg signed [5:0] s_prod;
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wire [2:0] u_pos_two = 3'b010;
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wire signed [2:0] s_pos_two = 3'sb010;
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wire signed [2:0] s_neg_two = 3'sb110;
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wire s = 1'b1; // flag to indicate signed
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wire u = 1'b0; // flag to indicate unsigned
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initial begin
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// unsigned positive two as first argument of multiply
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#1 s_prod = u_pos_two * u_pos_two;
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check_mult(1,u,u_pos_two,u,u_pos_two,s_prod,6'sb000100);
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#1 s_prod = u_pos_two * s_pos_two;
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check_mult(2,u,u_pos_two,s,s_pos_two,s_prod,6'sb000100);
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// This makes an unsigned result.
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#1 s_prod = u_pos_two * s_neg_two;
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check_mult(3,u,u_pos_two,s,s_neg_two,s_prod,6'sb001100);
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// signed positive two as first argument of multiply
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#1 s_prod = s_pos_two * u_pos_two;
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check_mult(4,s,s_pos_two,u,u_pos_two,s_prod,6'sb000100);
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#1 s_prod = s_pos_two * s_pos_two;
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check_mult(5,s,s_pos_two,s,s_pos_two,s_prod,6'sb000100);
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#1 s_prod = s_pos_two * s_neg_two;
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check_mult(6,s,s_pos_two,s,s_neg_two,s_prod,6'sb111100);
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// signed negative two as first argument of multiply
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// This makes an unsigned result.
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#1 s_prod = s_neg_two * u_pos_two;
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check_mult(7,s,s_neg_two,u,u_pos_two,s_prod,6'sb001100);
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#1 s_prod = s_neg_two * s_pos_two;
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check_mult(8,s,s_neg_two,s,s_pos_two,s_prod,6'sb111100);
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#1 s_prod = s_neg_two * s_neg_two;
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check_mult(9,s,s_neg_two,s,s_neg_two,s_prod,6'sb000100);
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if (failed_flag == 0)
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$display("PASSED");
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$finish;
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end
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task check_mult;
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input [31:0] idx;
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input signeda;
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input [ 2:0] arga;
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input signedb;
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input [ 2:0] argb;
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input [ 5:0] result,expected;
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if (result !== expected) begin
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failed_flag = 1;
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$write("failed: test %0d, ",idx);
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if (signeda)
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$write("3'sb%b",arga);
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else
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$write("3 'b%b",arga);
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$write(" * ");
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if (signedb)
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$write("3'sb%b",argb);
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else
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$write("3 'b%b",argb);
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$write(" = 6'sb%b (expected 6'sb%b)\n",result,expected);
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end
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endtask
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endmodule
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