35 lines
580 B
Verilog
35 lines
580 B
Verilog
/*
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* Notice how the port direction and type are declared
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* together in each statement.
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*/
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module one_a(sum,co,a,b,ci);
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output reg sum;
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output reg co;
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input wire a;
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input wire b;
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input wire ci;
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always@(a or b or ci)
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begin
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sum = a ^ b ^ ci;
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co = a*b || a*ci || b*ci;
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end
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endmodule
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module main;
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wire sum, co;
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reg [3:0] in;
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one_a dut (sum, co, in[0], in[1], in[2]);
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initial begin
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in = 0;
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#1 for (in = 0 ; in[3] == 0 ; in = in + 1) begin
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#1 $display("in=%b; co/sum = %b/%b", in, co, sum);
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end
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end
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endmodule // main
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