53 lines
820 B
Verilog
53 lines
820 B
Verilog
module main;
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real foo;
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real bar;
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initial begin
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foo = 1.0;
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bar = 1.2;
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if (foo >= bar) begin
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$display("FAILED -- foo < bar?");
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$finish;
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end
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if (foo >= 1.2) begin
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$display("FAILED -- foo < 1.2?");
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$finish;
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end
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if (1.0 >= 1.2) begin
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$display("FAILED -- 1.0 < 1.2?");
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$finish;
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end
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if (1 >= 1.2) begin
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$display("FAILED -- 1 < 1.2?");
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$finish;
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end
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if (foo > bar) begin
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$display("FAILED -- foo < bar?");
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$finish;
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end
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if (foo > 1.2) begin
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$display("FAILED -- foo < 1.2?");
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$finish;
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end
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if (1.0 > 1.2) begin
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$display("FAILED -- 1.0 < 1.2?");
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$finish;
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end
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if (1 > 1.2) begin
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$display("FAILED -- 1 < 1.2?");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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