28 lines
487 B
Verilog
28 lines
487 B
Verilog
module main;
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reg[63:0] period;
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initial begin
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if (period !== 'hx) $display ("init wrong");
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if (period === 'hx)
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$display ("init right");
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else
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$display ("init wrong 2: %h", period);
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end
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always @ (period) begin
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// if (period == 10) $display("%t hurrah!",$time);
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if (period !== 1'bx)
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$display ("right %t %d", $time,period);
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else
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$display("wrong %t %d",$time,period);
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end
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initial begin
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#10 period = $time;
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#30 $display("bye.");
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$finish(0);
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end
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endmodule
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