52 lines
761 B
Verilog
52 lines
761 B
Verilog
module ex1
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(
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clk,
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reset,
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insig,
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outsig
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);
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input clk;
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input reset;
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input [3:0] insig;
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output [3:0] outsig;
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reg [3:0] outsig;
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//reg [3:0] val_q;
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always @ ( insig ) begin
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outsig = ~(4'hf << insig);
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$display("out: %b, in: %b",outsig,insig);
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end
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endmodule
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module main;
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reg clk;
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reg reset;
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reg [3:0] insig;
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wire [3:0] outsig;
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ex1 ex1(
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.clk(clk),
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.reset(reset),
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.insig(insig),
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.outsig(outsig));
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initial
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begin
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$display ("\n starting the testbench\n");
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// set the inital value to 0
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clk = 1'b0;
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reset = 1;
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insig = 4'h0;
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#20 insig = 4'h2;
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end
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initial
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#71 $finish(0);
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always
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#10 clk = ~clk;
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always @(posedge clk)
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$display ($time, "..................clock tickling");
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endmodule
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