59 lines
936 B
Verilog
59 lines
936 B
Verilog
/*
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* The x in foo and bar should always have the same value.
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*/
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module foo();
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wire x;
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reg clk;
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reg [7:0] counter;
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always #5 clk <= ~clk;
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assign x = 0;
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initial begin
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clk = 0;
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counter = 0;
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# 2600 $display("PASSED");
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$finish;
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end
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always @(negedge clk)
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if (x !== u_bar.x) begin
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$display("FAILED -- x != u_bar.x");
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$finish;
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end
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always @(posedge clk) begin
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counter <= counter + 1;
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if (counter == 32)
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force x = 0;
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else if (counter == 64)
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force x = 1;
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else if (counter == 96)
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force x = 0;
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else if (counter == 128)
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release x;
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$display("[foo %d] x = %d",counter, x);
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end
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bar u_bar( .clk(clk), .x(x));
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endmodule
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module bar(clk, x);
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input clk;
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input x;
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reg [7:0] counter;
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initial counter = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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$display("[bar %d] x = %d",counter, x);
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end
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endmodule
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