30 lines
411 B
Verilog
30 lines
411 B
Verilog
module main;
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function [7:0] add;
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input [7:0] a, b;
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reg [8:0] tmp;
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begin
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tmp = a + b;
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if (tmp < 9'h100)
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add = tmp;
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else
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add = 8'hff;
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end
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endfunction // add
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reg[7:0] out;
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initial begin
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out = 1? add(8,9) : 0;
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if (out !== 8'd17) begin
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$display("FAILED -- out = %b", out);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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