44 lines
1.3 KiB
Verilog
44 lines
1.3 KiB
Verilog
//////////////////////////////////////////////////////////////////////////////
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//
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// using `timescale, test rounding up to specified precision and
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// scaling to specified time unit
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//
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// run with
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// iverilog lrm_eg.v
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// vvp a.out
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//
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// (uncomment $display statements for help in debugging)
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//
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//////////////////////////////////////////////////////////////////////////////
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`timescale 10 ns / 1 ns
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module test;
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reg set;
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parameter d = 1.55;
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reg fail;
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reg [7:0] ii;
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initial begin
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fail = 0;
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#d set = 0;
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//$display("time in units of 10ns: %0t, in ns: %0d, set: %0b",$time,ii,set);
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if((ii < 15) || (ii > 16)) fail = 1;
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#d set = 1;
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//$display("time in units of 10ns: %0t, in ns: %0d, set: %0b",$time,ii,set);
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if((ii < 31) || (ii > 32)) fail = 1;
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end
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initial begin
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//$dumpvars;
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for(ii = 0; ii < 50; ii = ii + 1) begin
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//$display("time in ns: %0d, set: %0b",ii,set);
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#0.1;
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end
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$display("\n\t\t**********************************************");
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if(fail) $display("\t\t********** timescale test FAILED *************");
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else $display("\t\t********** timescale test PASSED *************");
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$display("\t\t**********************************************\n");
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$finish(0);
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end
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endmodule
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