52 lines
2.3 KiB
Verilog
52 lines
2.3 KiB
Verilog
module example;
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reg [7:0] vec;
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reg [3:0] ix;
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wire vix = vec[ix];
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initial begin
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$display( " time ix vix vec" );
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$display( " ---- ---- --- --------" );
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$monitor( "%T %b %b %b", $time, ix, vix, vec );
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vec = 8'b00000000;
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ix = 0; // 0
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#100 ix = 1; // 100
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#100 ix = 2; // 200
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#100 ix = 3; // 300
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#100 ix = 4; // 400
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#100 ix = 5; // 500
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#100 ix = 6; // 600
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#100 ix = 7; // 700
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#100 ix = 8; // 800
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#100 ix = 4'b001x; // 900
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#100 ix = 4'b01x0; // 1000
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#100 ix = 4'b0x01; // 1100
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#100 ix = 0; // 1200
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#100 vec[ix] <= 1'b1; // 1300
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#100 vec[ix] <= 1'b0; // 1400
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#100 ix = 3; // 1500
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#100 vec[ix] <= 1'b1; // 1600
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#100 vec[ix] <= 1'b0; // 1700
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#100 ix = 6; // 1800
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#100 vec[ix] <= 1'b1; // 1900
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#100 vec[ix] <= 1'b0; // 2000
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#100 ix = 8; // 2100
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#100 vec[ix] <= 1'b1; // 2200
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#100 vec[ix] <= 1'b0; // 2300
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#100 ix = 4'b010x; // 2400
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#100 vec[ix] <= 1'b1; // 2500
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#100 vec[ix] <= 1'b0; // 2600
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#100 ix = 4'b00x1; // 2700
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#100 vec[ix] <= 1'b1; // 2800
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#100 vec[ix] <= 1'b0; // 2900
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#100 ix = 4'b0x10; // 3000
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#100 vec[ix] <= 1'b1; // 3100
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#100 vec[ix] <= 1'b0; // 3200
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#100 ix = 4'bxxxx; // 3300
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#100 vec[ix] <= 1'b1; // 3400
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#100 vec[ix] <= 1'b0; // 3500
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#100 $display( "Finish at time %T", $time );
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end
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endmodule
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