72 lines
1.4 KiB
Verilog
72 lines
1.4 KiB
Verilog
module whoever_wrote_this_should_be_shot ( Q, D, G );
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output Q;
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input D, G;
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wire Q_int;
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assign ( pull0, pull1 ) Q_int = Q_int;
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bufif1 buf_D ( Q_int, D, G );
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buf buf_Q ( Q, Q_int );
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endmodule
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module testbench;
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wire Q;
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reg D, G;
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whoever_wrote_this_should_be_shot uut ( Q, D, G );
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initial begin
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D = 1'b0;
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forever #5 D = ~ D;
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end
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initial begin
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G = 1'b0;
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forever #27 G = ~ G;
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end
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initial begin
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$monitor( $time,,,G,,,D,,,Q );
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// time 28: G=1, D=1, Q=1
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#28 if (Q !== 1) begin
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$display("FAILED -- Q should be 1, is %b", Q);
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$finish;
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end
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// time 31: G=1, D=0, Q=0
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#3 if (Q !== 0) begin
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$display("FAILED -- Q should be 0, is %b", Q);
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$finish;
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end
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// time 51: G=1, D=0, Q=0
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#20 if (Q !== 0) begin
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$display("FAILED -- Q should be 0, is %b", Q);
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$finish;
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end
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// time 56: G=0, D=1, Q=0
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#5 if (Q !== 0) begin
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$display("FAILED -- Q should be 0, is %b", Q);
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$finish;
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end
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// time 82: G=1, D=0, Q=0
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#26 if (Q !== 0) begin
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$display("FAILED -- Q should be 0, is %b", Q);
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$finish;
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end
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// time 86: G=1, D=1, Q=1
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#5 if (Q !== 1) begin
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$display("FAILED -- Q should be 1, is %b", Q);
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$finish;
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end
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#1000 $display("PASSED");
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$finish;
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end
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endmodule
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