60 lines
1.5 KiB
Verilog
60 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2002 Richard M. Myers
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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`timescale 10 ns/ 10 ns
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module top ;
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reg clk ;
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reg [11:0] x_os_integ, y_os_integ;
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reg [5:0] x_os, y_os;
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initial
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begin
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//$dumpfile("show_math.vcd");
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//$dumpvars(1, top);
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clk = 1'h0 ;
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x_os = 6'h01;
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y_os = 6'h3f;
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x_os_integ = 12'h000;
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y_os_integ = 12'h000;
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end
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initial
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begin
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#60;
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forever #3 clk = ~clk ; // 16Mhz
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end
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always @( posedge clk )
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begin
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// Integration period set above depending on configured modem speed.
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x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
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y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};
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$display ("%x %x", x_os_integ, y_os_integ);
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end
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initial
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begin
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#200 $finish(0);
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end
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endmodule
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