18 lines
339 B
Verilog
18 lines
339 B
Verilog
/*
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* This is the crux of PR487.
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*/
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module test();
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parameter[1:4] async_wrport = 4'b1100;
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reg async_wri;
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reg[1:4] async_i;
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initial begin
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for(async_i=1;async_i<=4;async_i=async_i+1) begin
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async_wri=async_wrport[async_i];
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$display("async_wrport[%d] --> %b", async_i, async_wri);
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end
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end
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endmodule
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