18 lines
350 B
Verilog
18 lines
350 B
Verilog
module pr3561350();
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reg [31:0] source;
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reg [31:0] result;
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initial begin
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source = 10;
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// the following expression results in a compiler internal error
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result = (source * 2) + 2 + 3 + 4;
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// check we get the expected result when the bug has been fixed
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if (result === 29)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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