26 lines
358 B
Verilog
26 lines
358 B
Verilog
module bug();
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reg [3:0] flags = 4'b0000;
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generate
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genvar i;
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for (i = 1; i < 4; i = i + 1) begin:loop
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localparam j = i;
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if (j > 0) begin
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initial #1 flags[j] = 1'b1;
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end
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end
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endgenerate
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initial begin
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#2 $display("flags = %b", flags);
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if (flags === 4'b1110)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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