45 lines
754 B
Verilog
45 lines
754 B
Verilog
`begin_keywords "1364-2005"
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`timescale 1ns/1ns
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module test;
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reg fail = 0;
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task check;
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input [10*8:1] expect;
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reg [10*8:1] s;
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begin
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$swrite(s, "Time %t", $time);
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$write("%s", s);
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if (s === expect)
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$display("");
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else
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begin
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$display(" != %s", expect);
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fail = 1;
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end
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end
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endtask
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initial
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begin
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$display("Test display formatting of time values");
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$timeformat(-6, 3, " us", 20);
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fork
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#0000 check(" 0.000 us");
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#0001 check(" 0.001 us");
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#0010 check(" 0.010 us");
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#0011 check(" 0.011 us");
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#0100 check(" 0.100 us");
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#0101 check(" 0.101 us");
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#1000 check(" 1.000 us");
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#1001 check(" 1.001 us");
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join
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$display("%s", fail? "FAILED" : "PASSED");
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end
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endmodule
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`end_keywords
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