43 lines
671 B
Verilog
43 lines
671 B
Verilog
module task_time_arg;
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reg pass;
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integer result;
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task test_it1;
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realtime tmp;
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begin
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tmp = $realtime;
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go_busy(tmp);
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end
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endtask
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task test_it2;
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go_busy($realtime);
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endtask
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task go_busy;
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input delay;
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integer delay;
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result = delay;
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endtask // go_busy
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initial begin
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pass = 1'b1;
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#6
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test_it1;
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if (result !== 6) begin
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$display("Failed: testit1, expected 6, got %d", result);
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pass = 1'b0;
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end
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#1
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test_it2;
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if (result !== 7) begin
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$display("Failed: testit2, expected 7, got %d", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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