46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
// Must be run with -gspecify
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module top;
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reg passed;
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reg a, b;
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wire y;
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initial begin
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passed = 1'b1;
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a = 0;
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b = 1;
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#2 if (y !== 1'bx && y !== 1'bz) begin
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$display("Failed: Initial value, expected 1'bx, got %b", y);
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passed = 1'b0;
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end
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#2 if (y !== 1'b0) begin
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$display("Failed: Initial value propagation, expected 1'b0, got %b", y);
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passed = 1'b0;
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end
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a = 1;
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#2 if (y !== 1'b0) begin
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$display("Failed: to hold initial value, expected 1'b0, got %b", y);
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passed = 1'b0;
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end
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#2 if (y !== 1'b1) begin
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$display("Failed: Final value propagation, expected 1'b1, got %b", y);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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my_and dut(y, a, b);
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endmodule
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module my_and(output wire y, input wire a, b);
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specify
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specparam ta = 1;
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specparam tb = 2;
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endspecify
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// A specparam is just like a parameter in this context. In reality
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// they can be overridden at run-time so the following should really
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// be an expression instead of just a constant 3, but for now 3 would
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// be acceptable. Specparams and the specify block need a major rework.
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assign #(ta+tb) y = a & b;
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endmodule
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