37 lines
497 B
Verilog
37 lines
497 B
Verilog
module connect(inout [1:0] c);
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tran(c[0], c[1]);
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endmodule
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module top();
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tri [3:0] a;
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reg dir;
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connect connect1(a[1:0]);
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connect connect2(a[2:1]);
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connect connect3(a[3:2]);
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assign a[0] = dir ? 1'bz : 1'b0;
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assign a[3] = dir ? 1'b1 : 1'bz;
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reg pass = 1;
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initial begin
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dir = 1'b0;
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#1 $display("%b", a);
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if (a !== 4'b0000) pass = 0;
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dir = 1'b1;
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#1 $display("%b", a);
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if (a !== 4'b1111) pass = 0;
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if (pass)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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