21 lines
486 B
Verilog
21 lines
486 B
Verilog
// Test that expression width calculation correctly treats right operand
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// of shift as unsigned regardless of its actual type.
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module test;
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reg pass;
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reg [8*20:1] str;
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reg signed [3:0] N;
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initial begin
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pass = 1'b1;
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N = -1;
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$sformat(str, "%0d", 1 << N);
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if (str[8*5:1] !== "32768" || str[8*20:8*5+1] !== 0) begin
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$display("FAILED test, expected \"32768\", got \"%0s\"", str);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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