80 lines
1.8 KiB
Verilog
80 lines
1.8 KiB
Verilog
// ivl-bugs PR#307
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module top;
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reg [127:0] in1;
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reg [127:0] in2;
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wire [128:0] out1;
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reg [128:0] out2;
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assign out1 = in1 + in2;
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task r;
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integer errors;
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begin
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out2 = in1 + in2;
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$display("\n %h\n+ %h", in1,in2);
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$display("= %h", out1);
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$display("= %h", out2);
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if (out1 != out2)
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begin
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$display("MISMATCH");
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errors = errors + 1;
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end
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end
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endtask
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initial begin
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r.errors = 0;
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in1 = 128'hffffffffffffffffffffffffffffffff;
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in2 = 128'hfffffffffffffffffffffffffffffff7;
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r;
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in1 = 128'hffffffffffffffffffffffffffffffff;
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in2 = 128'h00000000000000000000000000000001;
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r;
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in1 = 128'h00000000000000000000000000000001;
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in2 = 128'hffffffffffffffffffffffffffffffff;
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r;
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in1 = 128'h00000000000000000000000000000000;
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in2 = 128'hffffffffffffffffffffffffffffffff;
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r;
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in1 = 128'hffffffffffffffffffffffffffffffff;
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in2 = 128'hffffffffffffffffffffffffffffffff;
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r;
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in1 = 128'h00000000000000000000000000000000;
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in2 = 128'h00000000000000000000000000000000;
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r;
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in1 = 128'h80000000000000000000000000000000;
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in2 = 128'h80000000000000000000000000000000;
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r;
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in1 = 128'h08000000000000000000000000000000;
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in2 = 128'h08000000000000000000000000000000;
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r;
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in1 = 128'h00000000000000008000000000000000;
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in2 = 128'h00000000000000008000000000000000;
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r;
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in1 = 128'h55555555555555555555555555555555;
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in2 = 128'h55555555555555555555555555555555;
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r;
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in1 = 128'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
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in2 = 128'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
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r;
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if (r.errors)
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$display("FAILED: %d errors", r.errors);
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else
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$display("PASSED");
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end
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endmodule
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