86 lines
1.9 KiB
Verilog
86 lines
1.9 KiB
Verilog
/* Crash.v - reproduces a simulation-time crash (PLI assertion failure)
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Copyright: Bluespec, Inc. 2010
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License: GPLv2 or later
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Transcript:
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> uname -a
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Linux jnewbern-laptop 2.6.32-21-generic #32-Ubuntu SMP Fri Apr 16 08:09:38 UTC 2010 x86_64 GNU/Linux
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> iverilog -V
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Icarus Verilog version 0.9.2 (v0_9_2)
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...
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> iverilog -v -o crash -Wall Crash.v
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...
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/usr/lib/ivl/system.sft: Processing System Function Table file.
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/usr/lib/ivl/v2005_math.sft: Processing System Function Table file.
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/usr/lib/ivl/va_math.sft: Processing System Function Table file.
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Using language generation: IEEE1364-2005,no-specify,xtypes,icarus-misc
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PARSING INPUT
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LOCATING TOP-LEVEL MODULES
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Crash
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... done, 0 seconds.
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ELABORATING DESIGN
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... done, 0 seconds.
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RUNNING FUNCTORS
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-F cprop ...
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-F nodangle ...
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... 1 iterations deleted 0 dangling signals and 0 events.
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... 2 iterations deleted 0 dangling signals and 1 events.
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CALCULATING ISLANDS
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... done, 0 seconds.
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CODE GENERATION
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... invoking target_design
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... done, 0 seconds.
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STATISTICS
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lex_string: add_count=50 hit_count=17
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> ./crash
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VCD info: dumpfile dump.vcd opened for output.
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VCD warning: $dumpvars ignored, previously called at simtime 0
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vvp: vpi_priv.cc:165: PLI_INT32 vpi_free_object(__vpiHandle*): Assertion `ref' failed.
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Aborted
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*/
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module Crash();
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// Create clock
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reg CLK;
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initial begin
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CLK = 1'b0;
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end
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always begin
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#5;
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CLK = 1'b1;
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#5;
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CLK = 1'b0;
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end
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// Setup dumpfile at startup
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars;
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end
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// Count cycles
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reg [7:0] counter;
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initial begin
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counter = 8'd0;
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end
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always @(posedge CLK) begin
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counter <= counter + 1;
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end
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// Call system tasks on particular cycles
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always@(posedge CLK)
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begin
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if (counter == 8'd2) $dumpvars; // repeated!
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if (counter >= 8'd200) begin
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$display("PASSED");
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$finish(32'd0);
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end
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end
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endmodule
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