30 lines
671 B
Verilog
30 lines
671 B
Verilog
module top;
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reg pass;
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real rval;
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reg [7:0] res;
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initial begin
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pass = 1'b1;
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res = 6.0;
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if (res !== 8'd6) begin
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$display("Failed blocking assignment, expeted 6, got %d", res);
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pass = 1'b0;
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end
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// The compiler is generating bad code for a NB-assign with a real r-value.
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res <= 7.0;
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#1 if (res !== 8'd7) begin
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$display("Failed nonblocking assignment, expeted 7, got %d", res);
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pass = 1'b0;
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end
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rval = 8.0;
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res <= rval;
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#1 if (res !== 8'd8) begin
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$display("Failed nonblocking assignment, expeted 8, got %d", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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