34 lines
530 B
Verilog
34 lines
530 B
Verilog
module m;
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reg [15:0] x,y;
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initial
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begin
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y = 0;
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x <= 0;
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x <= 1;
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x <= 2;
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x <= 3;
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x <= 4;
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x <= 5;
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x <= 6; // Only this should cause an event, so y should become 1.
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#10
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$display("x = %d (expect 6)", x);
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$display("y = %d (expect 1)", y);
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if (x !== 16'd6) begin
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$display("FAILED");
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$finish;
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end
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if (y !== 16'd1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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always @(x[0])
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y <= y + 1;
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endmodule
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