75 lines
2.2 KiB
Verilog
75 lines
2.2 KiB
Verilog
module top;
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reg a, pass;
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wire x, y, ab;
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assign (weak1, weak0) x = (a === 1'b1) ? 1'b0 : 1'b1;
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assign y = a;
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// We need this since Icarus currently has a bug when forcing from
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// an expression (it only uses the value when the force ran).
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assign ab = ~a;
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tran (x, y);
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initial begin
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// $monitor ($realtime,, x,y,,a);
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pass = 1'b1;
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// Check matching values.
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#1 if ( x !== 1'bx || y !== 1'bx) begin
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$display("Failed initial value, expected 1'bx, 1'bx, got %b %b", x, y);
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pass = 1'b0;
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end
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#1 a = 1'b0;
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#1 if ( x !== 1'b0 || y !== 1'b0) begin
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$display("Failed same value, expected 1'b0, 1'b0, got %b %b", x, y);
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pass = 1'b0;
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end
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#1 a = 1'b1;
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#1 if ( x !== 1'b1 || y !== 1'b1) begin
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$display("Failed same value, expected 1'b1, 1'b1, got %b %b", x, y);
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pass = 1'b0;
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end
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// Check force with opposite values.
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#1 force x = ab;
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#1 if ( x !== 1'b0 || y !== 1'bx) begin
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$display("Failed force value, expected 1'b0, 1'bx, got %b %b", x, y);
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pass = 1'b0;
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end
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#1 a = 1'b0;
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#1 if ( x !== 1'b1 || y !== 1'bx) begin
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$display("Failed force value, expected 1'b1, 1'bx, got %b %b", x, y);
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pass = 1'b0;
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end
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// Now release.
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#1 release x;
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#1 if ( x !== 1'b0 || y !== 1'b0) begin
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$display("Failed release value, expected 1'b0, 1'b0, got %b %b", x, y);
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pass = 1'b0;
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end
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#1 a = 1'b1;
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#1 if ( x !== 1'b1 || y !== 1'b1) begin
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$display("Failed release value, expected 1'b1, 1'b1, got %b %b", x, y);
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pass = 1'b0;
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end
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// Now force and release the driving signal.
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#1 force a = 1'bx;
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#1 if ( x !== 1'bx || y !== 1'bx) begin
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$display("Failed driver value, expected 1'bx, 1'bx, got %b %b", x, y);
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pass = 1'b0;
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end
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#1 release a;
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a = 1'b0;
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#1 if ( x !== 1'b0 || y !== 1'b0) begin
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$display("Failed driver value, expected 1'b0, 1'b0, got %b %b", x, y);
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pass = 1'b0;
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end
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// Check that the other driver works.
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#1 a = 1'bz;
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#1 if ( x !== 1'b1 || y !== 1'b1) begin
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$display("Failed alt. value, expected 1'b1, 1'b1, got %b %b", x, y);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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