93 lines
2.0 KiB
Verilog
93 lines
2.0 KiB
Verilog
// This is the second part of a two-part test that checks that the argument to
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// a $signed or $unsigned function is treated as a self-determined expression.
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// This part performs tests where the argument is signed.
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module pr2922063b;
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reg signed [3:0] op1;
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reg signed [2:0] op2;
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reg [7:0] result;
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reg fail;
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task check_result;
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input [7:0] value;
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begin
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$write("Expected %b, got %b", value, result);
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if (result !== value) begin
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$write(" *");
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fail = 1;
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end
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$write("\n");
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end
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endtask
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initial begin
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fail = 0;
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$display("-- Addition tests --");
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op1 = 4'b1111; op2 = 3'b111;
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result = 8'sd0 + $signed(op1 + op2);
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check_result(8'b11111110);
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result = 8'sd0 + $unsigned(op1 + op2);
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check_result(8'b00001110);
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op1 = 4'b1000; op2 = 3'b011;
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result = 8'sd0 + $signed(op1 + op2);
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check_result(8'b11111011);
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result = 8'sd0 + $unsigned(op1 + op2);
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check_result(8'b00001011);
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$display("-- Multiply tests --");
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op1 = 4'b0101; op2 = 3'b100;
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result = 8'sd0 + $signed(op1 * op2);
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check_result(8'b11111100);
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result = 8'sd0 + $unsigned(op1 * op2);
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check_result(8'b00001100);
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op1 = 4'b0010; op2 = 3'b100;
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result = 8'sd0 + $signed(op1 * op2);
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check_result(8'b11111000);
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result = 8'sd0 + $unsigned(op1 * op2);
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check_result(8'b00001000);
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$display("-- Left ASR tests --");
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op1 = 4'b1010;
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result = 8'sd0 + $signed(op1 <<< 1);
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check_result(8'b00000100);
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result = 8'sd0 + $unsigned(op1 <<< 1);
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check_result(8'b00000100);
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op1 = 4'b0101;
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result = 8'sd0 + $signed(op1 <<< 1);
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check_result(8'b11111010);
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result = 8'sd0 + $unsigned(op1 <<< 1);
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check_result(8'b00001010);
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$display("-- Right ASR tests --");
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op1 = 4'b0101;
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result = 8'sd0 + $signed(op1 >>> 1);
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check_result(8'b00000010);
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result = 8'sd0 + $unsigned(op1 >>> 1);
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check_result(8'b00000010);
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op1 = 4'b1010;
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result = 8'sd0 + $signed(op1 >>> 1);
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check_result(8'b11111101);
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result = 8'sd0 + $unsigned(op1 >>> 1);
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check_result(8'b00001101);
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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