33 lines
652 B
Verilog
33 lines
652 B
Verilog
module bug;
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reg pass;
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reg [7:0] a, b;
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real r;
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initial begin
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pass = 1'b1;
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a = 8'd255;
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b = 8'd255;
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if ((a + b) != 254.0) begin
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$display("FAILED: addition != real constant.");
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pass = 1'b0;
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end
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r = 254.0;
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if ((a + b) != r) begin
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$display("FAILED: addition != real variable.");
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pass = 1'b0;
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end
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if ((a * b) != 1.0) begin
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$display("FAILED: multiplication != real constant.");
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pass = 1'b0;
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end
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r = 1.0;
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if ((a * b) != r) begin
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$display("FAILED: multiplication != real variable.");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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