36 lines
563 B
Verilog
36 lines
563 B
Verilog
module bug;
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function [1:0] Copy;
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input [1:0] Value;
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begin
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Copy = Value;
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end
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endfunction
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integer i;
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integer j;
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reg [1:0] Expect;
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reg [1:0] Actual;
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reg Failed;
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initial begin
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Failed = 0;
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for (i = 0; i < 4; i = i + 1) begin
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for (j = 0; j < 4; j = j + 1) begin
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Expect = (i%2)*2 + (j%2);
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Actual = Copy((i%2)*2 + (j%2));
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if (Actual !== Expect) begin
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$display("Failed: %0d,%0d expected %0d, got %0d", i, j, Expect, Actual);
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Failed = 1;
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end
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end
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end
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if (!Failed) $display("PASSED");
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end
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endmodule
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