27 lines
800 B
Verilog
27 lines
800 B
Verilog
module top;
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integer lp;
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wire signed [5:0] in = lp[5:0];
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// If these two are combined "$signed({1'b0,in[5]})" then this will work
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// as expected.
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wire [5:0] #1 base = (in + (in >>> 2)) >>> 2;
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wire signed [5:0] #1 fix = base + in[5];
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// wire [5:0] base; // If this is missing the program will core dump!
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// wire signed [5:0] #1 fix = ((in + (in >>> 2)) >>> 2) + $signed({1'b0,in[5]});
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wire [6:0] #1 res = in + fix;
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always @(*) $display("%0d: %d %d %d %d", $time, $signed(in), $signed(base),
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$signed(fix), $signed(res));
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// It appears that the final calculation event is being lost for fix == -1.
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initial begin
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lp = -7;
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#5 lp = -5;
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#1 lp = -6;
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#5 if ($signed(res) !== -7) $display("FAILED");
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else $display("PASSED");
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end
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endmodule
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