42 lines
722 B
Verilog
42 lines
722 B
Verilog
module pr2849783();
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reg i;
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wire a, b, c, d;
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assign a = i;
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assign b = a;
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assign c = 1;
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assign d = c;
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reg pass;
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initial begin
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i = 1;
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pass = 1;
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#1 $display("%b %b", a, b);
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if ((a !== 1) || (b !== 1)) pass = 0;
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#1 force a = 0;
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#1 $display("%b %b", a, b);
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if ((a !== 0) || (b !== 0)) pass = 0;
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#1 release a;
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#1 $display("%b %b", a, b);
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if ((a !== 1) || (b !== 1)) pass = 0;
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#1 $display("%b %b", c, d);
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if ((c !== 1) || (d !== 1)) pass = 0;
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#1 force c = 0;
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#1 $display("%b %b", c, d);
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if ((c !== 0) || (d !== 0)) pass = 0;
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#1 release c;
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#1 $display("%b %b", c, d);
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if ((c !== 1) || (d !== 1)) pass = 0;
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if (pass)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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